Integrated circuits (ICs) comprising many tens of thousands of semiconductor devices including field effect transistors (FETs) are a cornerstone of modern microelectronic systems. The various regions of the FETs (e.g. source/drain and source/drain extensions) are formed by introducing dopant atoms into a semiconductor substrate using methods such as ion implantation. After the dopants have been introduced, they are electrically activated by subjecting the semiconductor substrate to one or more annealing processes such as low temperature thermal anneal, rapid thermal anneal, spike anneal, flash anneal or laser anneal.
Unfortunately, dopants have a tendency to diffuse or expand both laterally and vertically away from the profile as-introduced during annealing thereby increasing the dimensions of the various device regions. This outward diffusion of dopants is undesirable particularly as semiconductor devices are scaled down in size.
For example, as the gate length of FETs is scaled down to 45 nm and beyond, the source and drain regions of the FET increasingly interact with the channel region, gaining influence on the channel potential. As a result, the gate electrode has reduced control over the on and off states of the channel. This effect is known as the short channel effect. In order to reduce the short channel effect, it is desirable to fabricate FET devices with shallower source/drain extension and/or source/drain junctions and also reduce the lateral extension of these regions after anneal.
Known approaches for the formation of ultra shallow junctions include the use of techniques such as pre-amorphization implant (PAI) to reduce the effect of ion channeling of dopant species. However, the PAI process commonly results in the formation of end of range (EOR) defects regions which include interstitial defects. Interstitials are undesirable as they have the effect of increasing junction depth and deactivating dopants during subsequent annealing steps. In addition, current leakage caused by residual EOR defects not removed by annealing processes is also becoming an important concern as device dimensions are scaled down to less than 100 nm.
In addition to the above-mentioned need for shallow junctions, the level of dopant activation is also a critical factor as device dimensions are scaled down. This is because the resistances of the various diffusion regions (e.g. source/drain regions) increase with the shrinking of diffusion region dimensions. Since an increase in the level of dopant activation has the effect of decreasing resistance, a higher level of dopant activation is desirable.
In view of the above discussion, there is a need for fabrication techniques that can mitigate at least one of the above mentioned problems.